Self-aligned dynamic threshold CMOS device

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United States of America Patent

PATENT NO 6159807
SERIAL NO

09157691

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Abstract

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A method of making a self-aligned dynamic threshold field effect device having a dynamic threshold voltage includes depositing a mandrel layer on the surface of an SOI substrate, then etching a gate opening in the mandrel layer. The gate opening is narrowed by depositing spacer material and a highly doped region, forming a low resistance body region, is created by ion implantation. The narrowed gate opening prevents the low resistance body from connecting the source/drain regions to be formed on opposite sides of the gate structure. A gate is formed by depositing a dielectric layer in the gate opening, and adding a layer of gate material, then chemical-mechanical polishing to the level of the mandrel layer, then removing the mandrel layer. Conventional processing is then used to create source/drain diffusion regions. The gate is connected to the body by creating a contact region at one end of the gate. The invention includes the device made by the method. The device needs less surface area than previous devices of this type due to the low resistance body and the connection region located at one end of the gate structure, and the method self-aligns the gate and the body region, while accurately controlling their relative sizes.

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Patent Owner(s)

Patent OwnerAddress
AURIGA INNOVATIONS INC303 TERRY FOX DRIVE SUITE 300 OTTAWA K2K 3J1

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bryant, Andres Essex Junction, VT 207 3297
Nowak, Edward J Essex Junction, VT 636 15371

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