Integrated circuit with selectively disabled logic blocks
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United States of America Patent
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-
Dec 12, 2000
Grant Date -
N/A
app pub date -
Jan 14, 1999
filing date -
Jan 14, 1999
priority date (Note) -
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status (Latency Note)
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Abstract
A method and circuit is provided for creating multiple product lines from a single silicon implementation of an integrated circuit (IC). Specifically, logic blocks within the IC are selectively disabled after manufacturing the IC to create various ICs of different functionality from a single silicon implementation of the IC. In one embodiment, a first logic block of the IC is coupled to a disable circuit by a first disable line and a second logic block of the IC is coupled to the disable circuit by a second disable line. The disable circuit can disable the first logic block by driving the first disable line to a disable logic state. Similarly, the disable circuit can disable the second logic block by driving the second disable circuit to the disable logic state. In an FPGA embodiment of the present invention, the first logic block is a row of configurable logic blocks (CLBs) and the second logic block is a column of CLBs.
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