Synchronous memory device of a wave pipeline structure
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United States of America Patent
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-
Dec 12, 2000
Grant Date -
N/A
app pub date -
May 26, 1999
filing date -
May 27, 1998
priority date (Note) -
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status (Latency Note)
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Abstract
A synchronous memory device of a wave pipeline structure includes: an internal clock signal generation means which generates an internal clock signal being a standard of an output data only during a period in which an output enable signal is activated; and a data transmission means which is connected between an output terminal of a plurality of registers and an output driver, is switched by a control of the internal clock signal, receives data stored in an activated register as input, and transmits the data to the output driver. As a result, the synchronous memory device greatly improves the data access path and the data output hold time, enhances the stability and performance of a memory operation, and achieves a high-speed operation.
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