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Abstract

The present invention proposes a method for fabricating shallow trench regions for isolation. An oxide hard mask is utilized for the silicon etching. A silicon oxynitride film is created near the trench corners to prevent the gate wrap-around and corner parasitic leakage. Forming trench regions on a semiconductor substrate by using a thick pad oxide layer as an etching hard mask. A thermal oxide film is grown to recover the etching damages. An undoped LPCVD amorphous silicon film is then deposited on entire surface of the semiconductor substrate. A high temperature/pressure oxidation process follows to convert the undoped amorphous silicon film into thermal oxide. A thick CVD oxide layer is deposited on the semiconductor substrate. The oxide film outside the trench regions is removed by using a CMP process. Finally, the MOS devices are fabricated on the semiconductor substrate by standard processes, and thus complete the present invention.

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First Claim