Semiconductor device with reduced thickness

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United States of America Patent

PATENT NO 6166443
SERIAL NO

09300683

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Abstract

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Internal electrodes and external lead wiring lines are formed on the front surface of a substrate of a semiconductor device, and solder bumps electrically connected to the external lead wiring lines via through holes are provided on the rear surface of the substrate. A first semiconductor chip is mounted on the surface of the substrate, and a second semiconductor chip is mounted on the rear surface of the substrate. Electrodes of the first semiconductor chip are connected to bonding pads at one side ends of the internal wiring lines, and electrodes of the second semiconductor chip are connected to the bonding pads at the other ends of the internal wiring lines and the external lead wiring lines with bonding wires passing through openings provided in the substrate. The solder bumps are formed with a height equal to or greater than the thickness of the second semiconductor chip so that, when the semiconductor device is mounted on an external mounting board or the like, a gap is formed between the substrate of the semiconductor device and the external mounting board by the height of the solder bumps themselves. The second semiconductor chip mounted on the rear surface of the substrate is accommodated in the gap.

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Patent Owner(s)

Patent OwnerAddress
NEC CORPORATION7-1 SHIBA 5-CHOME MINATO-KU TOKYO 108-8001 108-8001

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ichinose, Michihiko Tokyo, JP 10 183
Inaba, Takehito Tokyo, JP 12 145
Oyachi, Kenji Tokyo, JP 6 130

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