Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit
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United States of America Patent
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Dec 26, 2000
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N/A
app pub date -
Nov 3, 1999
filing date -
Nov 3, 1999
priority date (Note) -
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Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate (i) an internal select signal and (ii) a control signal in response to one or more chip select signals. The second circuit may be configured to generate a sleep signal in response to (i) said control signal and (ii) a clock signal.
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