Importance

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Abstract

A field programmable gate array with a matrix of rows and columns of programmable logic cells interconnectable to each other by a network of local and express bus lines and to I/O pads at the perimeter of the logic cell matrix and bus network, is characterized by having a set of clock lines which include main clock lines, column clock lines, and sector clock lines. Each of the main clock lines receives a different clock signal. Each of the column clock lines is associated with a particular column of logic cells of the matrix. Each column clock line is selectively connectable to any one of the main clock lines to receive a selected clock signal. Each of the sector clock lines is connected to a subset of the logic cells in a column. The column clock lines are selective connectable to the logic cells in this respective associated columns by means of the sector clock lines that are connectable to the column clock lines. A circuit for selectively inverting clock signals may be located along each sector clock line.

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First Claim