Method and apparatus for reducing standby leakage current using a transistor stack effect
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 2, 2001
Grant Date -
N/A
app pub date -
Sep 10, 1998
filing date -
Sep 10, 1998
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Reduction of standby leakage current in an internal circuit block using a transistor stack effect. For one embodiment, an apparatus includes a standby leakage reduction circuit to be coupled to the circuit block including a plurality of logic gates. The standby leakage reduction circuit causes a stack effect at each of the plurality of logic gates during a standby mode of the circuit block by turning off two or more series-coupled transistors of a same type (either n-type or p-type) at each of the plurality of logic gates.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully