Circuit and method for fully on-chip wafer level burn-in test
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United States of America Patent
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Jan 2, 2001
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N/A
app pub date -
May 24, 1999
filing date -
May 25, 1998
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Abstract
A circuit and method for conducting a fully on-chip wafer level burn-in test, which are adapted to generate, in a chip, a stress screen voltage required for a wafer burn-in test, based on an externally supplied voltage and an external control signal, namely, a wafer burn-in signal, thereby being capable of conducting a wafer burn-in test. The circuit includes a high voltage generating unit for receiving an external power supply voltage and generating a high voltage for gate oxide film failure screening for a cell in response to the received external power supply voltage, a pad on-chip unit for detecting a wafer burn-in signal and generating a wafer burn-in test mode entry signal upon detecting the wafer burn-in signal, a bit line pre-charge voltage generating unit for generating a bit line pre-charge voltage for the gate oxide film failure screening for the cell in response to the wafer burn-in test mode entry signal output from the pad on-chip unit, and a cell plate voltage generating unit for generating a cell plate voltage for capacitor failure screening for the cell in response to the wafer burn-in test mode entry signal.
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