Method and system for floorplanning a circuit design at a high level of abstraction
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United States of America Patent
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Jan 2, 2001
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N/A
app pub date -
Aug 29, 1997
filing date -
Aug 29, 1997
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Abstract
A method and a system implement a circuit design in an integrated chip. A floorplan of the circuit design is arranged at a high level of abstraction. The design is synthesized based on the floorplan, and the synthesized design is laid out physically on the integrated circuit.
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