FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA
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United States of America Patent
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-
Jan 9, 2001
Issued Date -
N/A
app pub date -
Feb 12, 1999
filing date -
Dec 30, 1997
priority date (Note) -
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status (Latency Note)
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Abstract
The present invention allows one portion of an FPGA to reconfigure another portion of the same FPGA. The invention makes use of input/output ports that can be connected on the input side to a frame register for loading configuration data into the FPGA. When a portion of the FPGA is to be reconfigured, data are loaded by a portion of the FPGA not being reconfigured into the frame register of the FPGA and addressed to the portion of the FPGA being reconfigured. Loading of the data is accomplished by forming a configuration data stream in the portion of the FPGA not being reconfigured, then applying the configuration data stream to an output buffer of the FPGA and forwarding that data to an input buffer that is connected to a frame register of the FPGA configuration structure.
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