Methods of testing integrated circuits to include data traversal path identification information and related status information in test data streams

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6173425
SERIAL NO

09060478

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

Methods of testing integrated circuits to include data traversal path identification information include the steps of transferring test data into an integrated circuit containing devices therein and then controlling operation of the integrated circuit so that the test data traverses a first path through the devices. At least a portion of the test data and an identification of at least a first portion of the first path are then retrieved from the integrated circuit. This retrieving step may be preceded by the step of overwriting a first portion of the test data with an identification of a first portion of the first path. In the case of a buffer memory device, an identification (e.g., address) of a current write register (receiving test data) may be 'tagged' to a series of test words written into the current write register during test mode operation. Similarly, when the test data is ultimately read from the buffer memory device, an identification of a current read register may be 'tagged' to the series of test words being read from the current read register. The tagged identification may be interleaved into the stream of test data being read from the current read register, may be overwritten into the stream or the address may be separately stored in the device and then provided (along with other path identification and status information) as a serial or parallel stream of identification data from a dedicated test I/O pad.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
INTEGRATED DEVICE TECHNOLOGY INC6024 SILVER CREEK VALLEY ROAD SAN JOSE CA 95138

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chin, Bruce Lorenz Duluth, GA 5 101
Knaack, Roland T Suwanee, GA 20 420

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation