Method of controlling gate dopant penetration and diffusion in a semiconductor device
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United States of America Patent
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Jan 16, 2001
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N/A
app pub date -
Mar 2, 1999
filing date -
Mar 2, 1999
priority date (Note) -
Expired
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Abstract
A method of forming a multi-layered dual-doped polysilicon structure that minimizes Boron penetration into the n+ polysilicon during formation of the p+ polysilicon. The method of the present invention also reduces the migration of Boron (p+ gate dopant) from the p+ polysilicon and the migration of Arsenic and/or Phosphorous (n+ gate dopant) from the n+ polysilicon during subsequent fabrication processing steps. The present invention is also directed to a semiconductor device having a gate dopant barrier that minimizes gate dopant penetration and migration.
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