Thermal vias-provided cavity-down IC package structure
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United States of America Patent
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Jan 16, 2001
Grant Date -
N/A
app pub date -
Mar 11, 1999
filing date -
Sep 30, 1998
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A thermal vias-provided cavity-down IC package structure of the invention is provided. The thermal vias-provided cavity-down IC package structure includes a substrate, a heat sink and an adhesive layer for attaching the substrate to the heat sink. The substrate is formed of multiple layers of printed circuit boards which are attached to each other, and have a cavity formed at the center thereof. A plurality of thermal vias is formed surrounding the substrate. The head sink is divided into a chip mount area and a thermal via joint area. The chip mount area is used for a chip mount pad to be disposed thereon, wherein a chip is connected to the heat sink through the chip mount pad. The thermal via area is electrically coupled to the thermal vias thereby to form an approximate short path or a short path. Thus, heat energy is transferred not only by the heat sink directly, but also from the heat sink to the substrate through the thermal vias. Furthermore, since the depth of the chip mount area is adjustable, it is unnecessary to additionally grind the chip, resulting in a great saving of time and cost.
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