Importance

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Abstract

A register associated with the architected logic queue of a memory-coherent device within a multiprocessor system contains a flag set whenever an architected operation--one which might affect the storage hierarchy as perceived by other devices within the system--is posted in the snoop queue of a remote snooping device. The flag remains set and is reset only when a synchronization instruction (such as the 'sync' instruction supported by the PowerPC.TM. family of devices) is received from a local processor. The state of the flag thus provides historical information regarding architected operations which may be pending in other devices within the system after being snooped from the system bus. This historical information is utilized to determine whether a synchronization operation should be presented on the system bus, allowing unnecessary synchronization operations to be filtered and additional system bus cycles made available for other purposes. When a local processor issues a synchronization instruction to the device managing the architected logic queue, the instruction is generally accepted when the architected logic queue is empty. Otherwise the architected operation is retried back to the local processor until the architected logic queue becomes empty. If the flag is set when the synchronization instruction is accepted from the local processor, it is presented on the system bus. If the flag is not set when the synchronization instruction is received from the local processor, the synchronization operation is unnecessary and is not presented on the system bus.

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First Claim