Importance

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Abstract

This invention is directed to a method and apparatus for producing video signal timing for a display device that has a display format different from the input video format. It also provides a method and apparatus for producing video signal timing in cases where the input video line rate and display output line rates are not the same. Furthermore, a method and apparatus are provided for synchronizing the display output line rate to the input line rate so that the source video line input rate can sustain the rate at which the input lines are processed to generate display video lines using a minimum amount of memory buffer for a variety of display processing methods. Another aspect of the present invention provides a method and apparatus for synchronizing display output timing to input video timing such that both are locked in terms of frame rate, but skewed in terms of frame phase, in order to accommodate latency incurred by processing of source video data to generate the display video data. A method and apparatus are also contemplated by this invention for adjusting the skew between the input source video frame timing and the display output video from timing to accommodate latency for various types of display processing such as, but not limited to, scaling, video format conversion, and filtering operations.

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First Claim