Semiconductor memory device, semiconductor device, and electronic apparatus using the semiconductor device
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United States of America Patent
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Jan 23, 2001
Grant Date -
N/A
app pub date -
Sep 28, 1999
filing date -
Dec 11, 1997
priority date (Note) -
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Abstract
A memory cell (1) with a MOS transistor (5) and a data-storing capacitor (7). One of two input/output electrodes of the MOS transistor (5) is connected to a bit line (36) and a gate electrode is connected to a word line (38). A first electrode (6) of the data-storing capacitor (7) is connected to the other input/output electrode of the MOS transistor (5) and a second electrode (14) is connected to a potential control circuit (40). When the data stored in the memory cell (1) is 'HIGH', the potential control circuit (40) changes the potential of the second electrode (14) of the data-storing capacitor (7) from a precharge potential VCC/2 to a ground potential GND after data-writing and data-readout operations are completed. When the data stored in the memory cell (1) is 'LOW', the potential control circuit (40) changes the potential of the second electrode (14) of the data-storing capacitor (7) from the precharge potential VCC/2 to a power potential VCC after data-writing and data-readout operations are completed.
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