Asynchronously addressable clocked memory device and method of operating same
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United States of America Patent
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-
Jan 23, 2001
Grant Date -
N/A
app pub date -
Sep 21, 1999
filing date -
Sep 21, 1999
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A timing circuit produces a clock signal. An address buffer circuit receives and stores a first address in a first latch and a second address in a second latch asynchronously with respect to the clock signal. A memory control circuit associated with an array of memory cells accesses a first memory cell in the array corresponding to the first address in a first clocked access cycle, and accesses a second memory cell in the array corresponding to the second address in a second clocked access cycle. If a further address is asynchronously received before said second access cycle, the further address replaces the second address in the second latch.
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