Multi-layer semiconductor devices with stress-relief profiles

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United States of America Patent

PATENT NO 6178189
SERIAL NO

09304441

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Abstract

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Multi-layer, semiconductor devices are configured to reduce stress by the removal of much of the structure which does not actually contribute to device performance. In one embodiment, trough between mesas which define light emitting facets in a laser diode bar are etched well into the substrate to remove all layers of different compositions there. In another embodiment, troughs are also etched in the backside of the substrate of a laser diode structure where the troughs are aligned along axes perpendicular to the axes of the mesas. The removal of stress permits more accurate alignment of the multiple facets along a single axis when the laser bar is bonded to a heat sink. The accurate alignment minimizes the placement constraints on the position of a microlens for achieving maximum power output and coupling efficiency for optical fibers coupled to the microlens.

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Patent Owner(s)

Patent OwnerAddress
OPTO POWER CORPORATION3321 E GLOBAL LOOP TUCSON AS 85706

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Patel, Rushikesh M Tucson, AZ 8 137
Srinivasan, Swaminathan Tucson, AZ 29 1501

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