Self-aligned silicided MOSFETS with a graded S/D junction and gate-side air-gap structure
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United States of America Patent
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Jan 30, 2001
Grant Date -
N/A
app pub date -
Dec 4, 1997
filing date -
Dec 4, 1997
priority date (Note) -
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Abstract
A MOSFET includes a gate oxide formed on a substrate. A thin dielectric layer is formed on the side walls of the gate. A gate is formed on the gate oxide. A first metal silicide layer is formed on top of the gate to increase the conductivity of the gate. Spacers are formed on the substrate and are separated with the gate by a space. Air gaps are formed between the gate and the spacers. First doped ion regions are formed aligned to the air gaps in the substrate, under a portion of the dielectric layer. Second doped ion regions are formed under the spacers in the substrate, next to the first doped ion regions. Third doped ion regions are formed in the substrate next to the second doped ion regions. The third doped ion regions have relatively highly doped ions to the first doped ion regions. The second doped ion regions are formed with immediately highly doped ions between the first and the third doped ion regions.
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