Programmable logic device with highly routable interconnect
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United States of America Patent
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Jan 30, 2001
Grant Date -
N/A
app pub date -
Jan 6, 1998
filing date -
Apr 10, 1994
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Abstract
A programmable logic device architecture with a highly routable programmable interconnect structure. The arrangement of the logic array blocks (LABs), programmable interconnect structure, and other logical elements forms a Clos network. After specific constraints have been met, the architecture is guaranteed to route. The architecture is provably routable when there is no fan-out in the middle stage. A LAB (200) comprises an input multiplexer region (504), logic elements (300), input-output pins (516), and output multiplexer region (508).
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