Importance

Loading Importance Indicators...

Abstract

A structure and method for implementing an EEPROM array using 2-bit non-volatile memory cells arranged in a plurality of rows and columns. Each memory cell has a first charge trapping region for storing a first bit and a second charge trapping region for storing a second bit. A plurality of bit lines are provided, wherein each bit line is coupled to the first charge trapping region of each memory cell in one column and to the second charge trapping region of each memory cell in an adjacent column. A memory control circuit is coupled to the bit lines, wherein the memory control circuit erases a word stored in the EEPROM array by applying an erase voltage to one or more of the bit lines. The applied erase voltage erasing all of the charge trapping regions coupled to the one or more bit lines. All of the charge trapping regions erased in response to the erase voltage represent a single word of the EEPROM array. The memory control circuit reads a word stored in the EEPROM array by sequentially accessing all of the charge trapping regions coupled to one or more of the bit lines. Similarly, the memory control circuit writes a word to the EEPROM array by sequentially programming all of the charge trapping regions coupled to one or more of the bit lines.

Loading the Abstract Image...

First Claim