Importance

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Abstract

Nonvolatile integrated circuit memory devices include a memory cell array having a plurality of rows of memory cells therein that are electrically coupled to respective word lines. A word line driver circuit is provided having a plurality of outputs electrically coupled to the word lines. A preferred voltage supply control circuit is also provided. This voltage supply control circuit is responsive to a verify enable signal and a flag signal and powers the word line driver circuit at a first voltage level when the verify enable signal is inactive or the flag signal is active, and powers the word line driver circuit at a second voltage level greater than the first voltage level when the verify enable signal is active and the flag signal is inactive. The first voltage level corresponds to a power supply voltage level Vcc and the second voltage level corresponds to a boosted voltage level Vpp having a magnitude that exceeds a magnitude of the power supply voltage level Vcc. The memory device also comprises a program/erase verification control circuit that generates an active verify enable signal continuously during a verification time interval and generates an active flag signal as a series of pulses during the verification time interval. Because the generation of an active flag signal results in the generation of a word line voltage having reduced magnitude, smaller pull-down transistors can be used within the word line driver circuit and higher integration densities can therefore be achieved.

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First Claim