US Patent No: 6,184,463

Number of patents in Portfolio can not be more than 2000

Integrated circuit package for flip chip

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Importance

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Abstract

An integrated circuit package includes a ceramic substrate having a cut out configured to receive a flip chip. The cut out includes vias formed as through holes. A flip chip is received within the cut out of the ceramic substrate and has conductive bumps formed thereon corresponding to the electrical input/output contacts of the flip chip. The conductive bumps are received within the through holes of the ceramic substrate. A second integrated circuit chip is mounted on the flip chip in back-to-back relationship. A controlled impedance line is secured to the conductive bumps and acts as a coax. In another aspect of the present invention, a heat sink can be mounted on the back of the flip chip, and the second integrated circuit chip mounted on the heat sink.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
HARRIS CORPORATIONMELBOURNE, FL1841

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Newton, Charles M Palm Bay, FL 39 410
Panchou, Karen A Grant, FL 4 147

Cited Art

Patent Info (Count) # Cites Year
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (3)
5,081,563 Multi-layer package incorporating a recessed cavity for a semiconductor chip 125 1990
5,635,761 Internal resistor termination in multi-chip module environments 30 1994
5,940,687 Wire mesh insert for thermal adhesives 6 1997
 
FREESCALE SEMICONDUCTOR, INC. (2)
5,019,673 Flip-chip package for integrated circuits 93 1990
5,371,404 Thermally conductive integrated circuit package with radio frequency shielding 249 1993
 
KABUSHIKI KAISHA TOSHIBA (2)
5,461,197 Electronic device having a chip with an external bump terminal equal or smaller than a via hole on a board 63 1994
5,488,542 MCM manufactured by using thin film multilevel interconnection technique 54 1994
 
KYOCERA AMERICA, INC. (2)
5,134,246 Ceramic-glass integrated circuit package with integral ground and power planes 11 1991
5,258,575 Ceramic glass integrated circuit package with integral ground and power planes 15 1991
 
AT&T Bell Laboratories (1)
4,577,214 Low-inductance power/ground distribution in a package for a semiconductor chip 69 1984
 
FRESH QUEST CORPORATION (1)
5,589,781 Die carrier apparatus 73 1993
 
FUJITSU LIMITED (1)
5,854,534 Controlled impedence interposer substrate 99 1995
 
INSTITUTE OF MICROELECTRONICS (1)
5,925,934 Low cost and highly reliable chip-sized package 120 1996
 
INTEL CORPORATION (1)
5,815,372 Packaging multiple dies on a ball grid array substrate 126 1997
 
LUCENT TECHNOLOGIES INC. (1)
6,087,732 Bond pad for a flip-chip package 18 1998
 
MICRO LINEAR CORPORATION (1)
5,545,924 Three dimensional package for monolithic microwave/millimeterwave integrated circuits 34 1993
 
MOTOROLA, INC. (1)
5,438,224 Integrated circuit package having a face-to-face IC chip arrangement 169 1993
 
NATIONAL SEMICONDUCTOR CORPORATION (1)
5,663,593 Ball grid array package with lead frame 71 1995
 
NGK SPARK PLUG CO., LTD. (1)
5,196,089 Multilayer ceramic substrate for mounting of semiconductor device 7 1991
 
Olin Corporation (1)
4,862,323 Chip carrier 16 1985
 
ROUND ROCK RESEARCH, LLC (1)
5,811,879 Stacked leads-over-chip multi-chip module 195 1997

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
AMKOR TECHNOLOGY, INC. (55)
6,414,396 Package for stacked integrated circuits 26 2000
6,395,578 Semiconductor package and method for fabricating the same 184 2000
6,452,278 Low profile package for plural semiconductor dies 40 2000
6,798,049 Semiconductor package and method for fabricating the same 36 2000
6,552,416 Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring 29 2000
6,642,610 Wire bonding method and semiconductor package manufactured using the same 20 2000
6,762,078 Semiconductor package having semiconductor chip within central aperture of substrate 20 2001
6,759,737 Semiconductor package including stacked chips with aligned input/output pads 34 2001
6,967,124 Imprinted integrated circuit substrate and method for imprinting an integrated circuit substrate 10 2001
6,784,534 Thin integrated circuit package having an optically transparent window 16 2002
6,982,485 Stacking structure for semiconductor chips and a semiconductor package using it 7 2002
6,576,998 Thin semiconductor package with semiconductor chip and electronic discrete device 6 2002
6,995,448 Semiconductor package including passive elements and method of manufacture 11 2002
6,683,795 Shield cap and semiconductor package including shield cap 50 2002
7,042,072 Semiconductor package and method of manufacturing the same which reduces warpage 0 2002
6,747,352 Integrated circuit having multiple power/ground connections to a single external terminal 4 2002
6,717,248 Semiconductor package and method for fabricating the same 10 2002
6,803,254 Wire bonding method for a semiconductor package 6 2003
6,982,488 Semiconductor package and method for fabricating the same 18 2003
7,190,071 Semiconductor package and method for fabricating the same 4 2004
7,061,120 Stackable semiconductor package having semiconductor chip within central through hole of substrate 9 2004
7,185,426 Method of manufacturing a semiconductor package 85 2004
RE40112 Semiconductor package and method for fabricating the same 0 2004
7,145,238 Semiconductor package and substrate having multi-level vias 9 2004
7,399,661 Method for making an integrated circuit substrate having embedded back-side access conductors and vias 4 2004
7,312,103 Method for making an integrated circuit substrate having laser-embedded conductive patterns 5 2004
7,334,326 Method for making an integrated circuit substrate having embedded passive components 7 2005
7,211,900 Thin semiconductor package including stacked dies 7 2005
7,297,562 Circuit-on-foil process for manufacturing a laminated semiconductor package substrate having embedded conductive patterns 13 2005
7,633,765 Semiconductor package including a top-surface metal layer for implementing circuit features 35 2005
7,548,430 Buildup dielectric and metallization process and semiconductor package 18 2006
7,501,338 Semiconductor package substrate fabrication method 0 2006
7,365,006 Semiconductor package and substrate having multi-level vias fabrication method 3 2006
7,589,398 Embedded metal features structure 1 2006
7,671,457 Semiconductor package including top-surface terminals for mounting another semiconductor package 18 2006
7,550,857 Stacked redistribution layer (RDL) die assembly package 18 2006
7,750,250 Blind via capture pad structure 1 2006
7,752,752 Method of fabricating an embedded circuit pattern 2 2007
8,323,771 Straight conductor blind via capture pad structure and fabrication method 0 2007
7,670,962 Substrate having stiffener fabrication method 2 2007
8,322,030 Circuit-on-foil process for manufacturing a laminated semiconductor package substrate having embedded conductive patterns 0 2007
8,316,536 Multi-level circuit substrate fabrication method 0 2008
7,960,827 Thermal via heat spreader package and method 1 2009
8,341,835 Buildup dielectric layer having metallization pattern semiconductor package fabrication method 0 2009
7,825,520 Stacked redistribution layer (RDL) die assembly package 3 2009
8,222,538 Stackable via package and method 0 2009
7,911,037 Method and structure for creating embedded metal features 0 2009
8,018,068 Semiconductor package including a top-surface metal layer for implementing circuit features 1 2009
8,110,909 Semiconductor package including top-surface terminals for mounting another semiconductor package 0 2010
8,300,423 Stackable treated via package and method 0 2010
8,294,276 Semiconductor device and fabricating method thereof 0 2010
8,026,587 Semiconductor package including top-surface terminals for mounting another semiconductor package 0 2010
8,203,203 Stacked redistribution layer (RDL) die assembly package 0 2010
8,337,657 Mechanical tape separation package and method 0 2010
8,227,338 Semiconductor package including a top-surface metal layer for implementing circuit features 0 2011
 
INFINEON TECHNOLOGIES AG (2)
7,727,799 Integrated circuit package 1 2005
8,102,041 Integrated circuit package 0 2010
 
INTEL CORPORATION (2)
6,696,320 Low profile stacked multi-chip package and method of forming same 6 2001
7,009,300 Low profile stacked multi-chip package and method of forming same 3 2003
 
SEIKO EPSON CORPORATION (2)
6,424,050 Semiconductor device 38 2000
7,183,619 Surface acoustic wave apparatus 2 2004
 
FREESCALE SEMICONDUCTOR, INC. (1)
6,916,682 Semiconductor package device for use with multiple integrated circuits in a stacked configuration and method of formation and testing 10 2001
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (1)
6,404,648 Assembly and method for constructing a multi-die integrated circuit 47 2001
 
LINEAR SIGNAL, INC. (1)
8,195,118 Apparatus, system, and method for integrated phase shifting and amplitude control of phased array signals 0 2009
 
MICRON TECHNOLOGY, INC. (1)
8,384,200 Semiconductor device assemblies including face-to-face semiconductor dice and systems including such assemblies 0 2006
 
STATS CHIPPAC LTD. (1)
7,750,482 Integrated circuit package system including zero fillet resin 0 2006
 
TEXAS INSTRUMENTS INCORPORATED (1)
8,338,229 Stackable plasma cleaned via package and method 0 2010
 
UTAC HONG KONG LIMITED (1)
6,790,710 Method of manufacturing an integrated circuit package 17 2002