Design method for compensation of process variation in CMOS digital input circuits

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United States of America Patent

PATENT NO 6184704
SERIAL NO

09246294

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Abstract

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This invention describes an improved design of CMOS. digital input circuits. This improvement reduces the switching level uncertainty range and thus increases the noise margin, compensating for manufacturing process variations. This improvement is achieved by providing resistive compensation devices in series with the P-type and the N-type CMOS transistors in the first stage of a multistage digital input circuit. These resistive devices can be implemented by means of resistors or by means of MOSFET devices which provide the required resistive function. These compensation devices modify the input-output voltage transfer characteristics of the first stage so as to reduce the switching level variation at the input to the circuit. The resulting digital input circuit has a greater tolerance to input noise levels. The improvement provided by this invention is particularly important as integrated circuits design trend is to operate with lower supply voltages.

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Patent Owner(s)

Patent OwnerAddress
CIRRUS LOGIC INC800 WEST 6TH STREET AUSTIN TX 78701

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hu, Yu David Singapore, SG 1 4
Oei, Chan Chee Singapore, SG 3 25
Wang, Hongwei Singapore, SG 120 282

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