Importance

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Abstract

A programmable logic device (PLD) which includes a dedicated composable RAM array having a plurality of memory tiles. The PLD also includes an array of CLBs, wherein each of the CLBs in the array is coupled to a corresponding one of the memory tiles. The composable RAM array is accessed through the CLBs. That is, the input signals required by the memory tiles are routed through the corresponding CLBs. Similarly, the output signals provided by the memory tiles are routed out through the corresponding CLBs. Each CLB can be configured to operate as a conventional CLB (i.e., ignore its corresponding memory tile). Alternatively, each CLB can be configured to provide an interface to its corresponding memory tile. To help achieve this, each CLB comprises a set of multiplexers for selectively routing data output signals provided by the corresponding memory tile or output signals provided by the CLB. In addition, each memory tile is capable of being selectively coupled to one or more adjacent memory tiles, thereby allowing the size of the composable RAM array to be selected by the circuit designer. This capability also allows the composable RAM array to be configured to form a plurality of separate and independent memories.

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First Claim