Shallow trench isolation process

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United States of America Patent

PATENT NO 6187649
SERIAL NO

09348409

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Abstract

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A shallow trench isolation process is described. A pad oxide layer is formed over a substrate. A silicon nitride layer is formed over the pad oxide layer. The silicon nitride layer is patterned. The pad oxide layer and the substrate are etched using the patterned silicon nitride as an etching mask, and thus a trench is formed in the substrate. A liner oxide layer is grown over the trench. An oxide layer is deposited to fill the trench in the substrate and has a surface level higher than the silicon nitride layer. The oxide layer is polished to partially remove the oxide layer over the silicon nitride layer. The silicon nitride layer is removed from the substrate, by which removal the oxide layer has an exposed sidewall. A polysilicon spacer is formed on the exposed sidewall. The pad oxide layer is removed. The polysilicon spacer is oxidized and transformed into an oxide spacer.

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Patent Owner(s)

Patent OwnerAddress
UNITED MICROELECTRONICS CORPNO 3 LI-HSIN RD II SCIENCE-BASED INDUSTRIAL PARK HSINCHU

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gau, Jing-Horng Hsinchu Hsien, TW 36 211

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