FPGA one turn routing structure using minimum diffusion area
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United States of America Patent
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-
Feb 13, 2001
Grant Date -
N/A
app pub date -
Jul 16, 1998
filing date -
Dec 5, 1996
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A structure and method are provided for designing the architecture of a routing structure in a programmable logic device that maximizes the number of possible paths for an available diffusion area. The method comprises steps for selecting wire directions for a plurality of wires interconnectible at a unitary diffusion area of an integrated circuit device or portion thereof. The steps of the inventive method result in a highly alternated array of wire directions, including serial sets of four wires composed of four wires extending in four compass directions. In one embodiment of the inventive method, the first two wire directions are repeated from set to set, while the second two wire directions are alternated. A second embodiment with a repeating pattern of 24 wire directions is also disclosed.
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