Importance

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Abstract

A reset device is disclosed which is part of a micro-controller formed on an integrated circuit. The reset device has a counter which outputs a count enable signal after counting a predetermined number of counts. In response to an input reset signal, an input device of the reset device provides a start signal to the counter for initiating count-down thereof. An output device outputs an output reset signal in response to the start signal and the count enable signal. The start signal is inhibited by a control signal, which is provided from a control device in response to an external reset signal received at an input pin of the micro-controller. The input device includes an AND gate which receives the input reset signal, an inverted delayed version of the input reset signal, and the disable signal. The reset device further includes an OR gate which receives the start signal and the count enable signal to provide an input signal to the output device for generation of the output reset signal. Another OR gate receives the outputs the counter and provides the count enable signal.

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First Claim