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Abstract

A content-addressable memory (CAM) cell uses only n-channel (NMOS) transistors. A total of six transistors (6T) are used in the cell. Dynamic storage and differential sensing are used. A pair of bit lines carry true and complement data. A word line connected to the gates of pass transistors couples the bit lines to gates of storage transistors. The sources of the storage transistors are grounded. Charge is dynamically stored on the gates of the storage transistors when the pass transistors are turned off. One storage transistor has a gate charged to a high voltage and is thus on, while the other storage transistor has its gate discharged to a low voltage and is thus off. The drains of the storage transistors are connected to a match line through a pair of match transistors. The gates of the match transistors are connected to the bit lines. During a compare operation, the test data and its complement are applied to the bit lines, turning one of the match transistors on and the other off. The match transistors and storage transistors form two series connections to the match line. When both a match transistor and a storage transistor in series are on, the match line is discharged, indicating a mismatch. An exclusive-OR (XOR) function is performed by the match and storage transistors. The match transistors can be cross-connected to the opposite bit lines to match data polarity for writes.

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