Performance monitoring of cache misses and instructions completed for instruction parallelism analysis
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United States of America Patent
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Feb 13, 2001
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N/A
app pub date -
Dec 17, 1996
filing date -
Dec 17, 1996
priority date (Note) -
Expired
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Abstract
A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.
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