Method of forming power semiconductor devices having overlapping floating field plates for improving breakdown voltage capability
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United States of America Patent
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Feb 20, 2001
Grant Date -
N/A
app pub date -
Dec 12, 1997
filing date -
Feb 29, 1996
priority date (Note) -
In Force
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Abstract
Power semiconductor devices having overlapping floating field plates include a primary field plate and a plurality of floating field plates which are formed on an electrically insulating region and capacitively coupled together in series between an active region of a power semiconductor device and a floating field ring. Preferably, the capacitive coupling is achieved by overlapping at least portions of the floating field plates. According to one embodiment, a power semiconductor device comprises a semiconductor substrate having a first region of first conductivity type therein extending to a face thereof and a second region of second conductivity type in the first region of first conductivity type and forming a P-N junction therewith. To improve the breakdown characteristics of the P-N junction, an electrically insulating region is provided on the face and a primary field plate is formed on an upper surface of the electrically insulating region and in contact with the second region of second conductivity type. In addition, a first dielectric region (e.g., SiO.sub.2) is provided on an upper surface of the electrically insulating region and on an upper surface of the primary field plate. A first floating field plate is formed on an upper surface of the electrically insulating region and on an upper surface of the first dielectric region extending opposite and overlapping the primary field plate. A second dielectric region is provided on the upper surface of the electrically insulating region and on an upper surface of the first floating field plate. A second floating field plate is also provided on the upper surface of the electrically insulating region and on an upper surface of the second dielectric region extending opposite and overlapping the first floating field plate.

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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
FAIRCHILD KOREA SEMICONDUCTOR LTD | 82-3 DODANG-DONG WONMI-KU PUCHON KYUNGKI-DO |
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Seok, Kyung-Wook | Seoul, KR | 3 | 71 |
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Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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