Method for fabricating of super self-aligned bipolar transistor
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United States of America Patent
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Feb 20, 2001
Issued Date -
N/A
app pub date -
Jan 13, 1999
filing date -
Nov 27, 1996
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth process without using a trench for isolating between elements. According to the invention, isolation between elements is derived by using a mask defining an emitter region and a second spacer. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth for a base is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.
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