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Abstract

An integrated circuit having an embedded testing system. The integrated circuit has a plurality of chip input terminals and a plurality of chip output terminals and operates in a test mode and a normal mode. The integrated circuit includes a plurality of core modules and a test data bus. The test data bus has first and second conductors accessible from the chip input and output terminals, respectively. Each core module includes an access register for storing an access word, and a plurality of registers connected together as a first scan-chain having an input terminal for receiving data to be shifted into the registers and an output terminal for reading data shifted out of the registers. Each core module also includes a scan-in enable circuit and a scan-out enable circuit. The scan-in enable circuit connects the input terminal of the first scan-chain to the first conductor of the test data bus. The scan-out enable circuit connects the output terminal of the first scan-chain to an output terminal associated with the core module. The access word determines the connections and the operations carried out by the core module in the test mode. The access registers of the core modules are connected together to form an access scan-chain having an input terminal accessible from one of the chip input terminals. One of the core modules has an output terminal connected to the second conductor of the test data bus. Core modules may also include other scan-chains used in the testing hardware. In such modules, the scan-in enable and scan-out enable circuits include circuitry for selecting the scan-chain connections to the test data bus and the output terminal of the core module.

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