Method and apparatus for reducing standby leakage current using input vector activation
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United States of America Patent
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Feb 20, 2001
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N/A
app pub date -
Sep 10, 1998
filing date -
Sep 10, 1998
priority date (Note) -
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Abstract
A technique for reducing standby leakage current in a circuit block using input vector activation. A complex circuit includes a plurality of inputs and one or more transistor stacks. At least some of the transistor stacks are coupled to at least one of the inputs. The circuit also includes logic to apply a selected input vector to the plurality of inputs during a standby mode. The input vector is selected based on a configuration of the one or more transistor stacks in the circuit block to turn off a first number of transistors in the transistor stacks. The first number is within a selected percent of a maximum number of transistors in the transistor stacks that can be turned off by any vector applied at the plurality of inputs.
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