Method of expanding bus loading capacity
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United States of America Patent
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Feb 27, 2001
Grant Date -
N/A
app pub date -
Oct 1, 1997
filing date -
May 13, 1997
priority date (Note) -
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Abstract
A method for expanding the loading capacity of a PCI bus in an information processing system having a multiple bus architecture. In one embodiment, the method comprises connecting a processor-to-PCI bridge to a plurality of PCI-to-PCI bridges to generate multiple PCI buses. A plurality of add-in board connectors are coupled to each of the generated PCI buses. In another embodiment, the method comprises connecting two or more processor-to-PCI bridges to a plurality of PCI-to-PCI bridges to generate multiple PCI buses. The resulting system expands the loading capacity of a PCI bus while adding fault-tolerance and resistance to single point failures.
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