Mapping heterogeneous logic elements in a programmable logic device
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United States of America Patent
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Feb 27, 2001
Grant Date -
N/A
app pub date -
Oct 9, 1998
filing date -
Oct 17, 1997
priority date (Note) -
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Abstract
A method and mechanism for mapping heterogeneous logic elements in a portion of electronic design compilation for a programmable integrated circuit is disclosed. Specifically, the invention provides a method to perform the technology mapping of heterogeneous logic elements in a programmable logic device such as selectively choosing the best combination of product term logic elements and look up table logic elements.
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