Wafer level packaging method and devices formed
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United States of America Patent
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Mar 6, 2001
Grant Date -
N/A
app pub date -
Mar 23, 1999
filing date -
Mar 23, 1999
priority date (Note) -
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status (Latency Note)
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Abstract
The present invention discloses a method for forming a wafer level package by first providing a silicon wafer that has a multiplicity of IC dies formed on a top surface, each of the IC dies has at least one peripheral I/O pad formed in an insulating layer, then forming at least one via plug of a conductive metal with a top surface exposed on the at least one peripheral I/O pad, then coating a layer of an insulating material that has sufficient elasticity on the surface of the wafer prior to the deposition and forming of a metal trace on the elastic material layer, at least one area array I/O pad is then formed at an opposite end of the metal trace with a solder bump formed on the I/O pad before they are reflowed into a solder ball. The elastic material layer deposited under the metal traces acts as a stress-buffing layer such that an IC circuit of high reliability can be produced on a wafer level for the low cost fabrication of IC assembly.
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