Importance

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Abstract

A technique for integrating an internal clock signal with various function commands in an integrated circuit device having an externally supplied clock signal to create a set of command clocks which have the same rising (or falling) edge time, duty cycle and duration and are, therefore, inherently clocked to ameliorate signal 'race' and 'skew' conditions encountered in prior designs. The technique of the present invention, therefore, improves overall device operational speeds in executing commands by reducing internal gate delays and resulting in faster data access times in integrated circuit memory devices such as synchronous dynamic random access memory ('SDRAM') devices. Moreover, because the resultant design provides faster operation times, lower cost process technologies may be utilized to achieve substantially comparable performance levels.

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First Claim