Processor-cache protocol using simple commands to implement a range of cache configurations
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United States of America Patent
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Mar 13, 2001
Grant Date -
N/A
app pub date -
May 6, 1997
filing date -
Nov 25, 1996
priority date (Note) -
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Abstract
A computer system having a processor-cache protocol supporting multiple cache configurations is described. The computer system has a processor having a cache control circuit to control multiple cache memory circuits. The processor including its cache control circuit is coupled to a cache bus. A second level cache memory is also coupled to the cache bus. The cache control circuit controls the second level cache by issuing commands that are executed by the second level cache.
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