Shared cache structure for temporal and non-temporal information using indicative bits
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United States of America Patent
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Mar 13, 2001
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N/A
app pub date -
Mar 31, 1998
filing date -
Mar 31, 1998
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Abstract
A method and system for providing cache memory management. The system comprises a main memory, a processor coupled to the main memory, and at least one cache memory coupled to the processor for caching of data. The at least one cache memory has at least two cache ways, each comprising a plurality of sets. Each of the plurality of sets has a bit which indicates whether one of the at least two cache ways contains non-temporal data. The processor accesses data from one of the main memory or the at least one cache memory.
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