Method and apparatus for testing field programmable gate arrays
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United States of America Patent
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Mar 13, 2001
Grant Date -
N/A
app pub date -
Jun 30, 1998
filing date -
Jun 30, 1998
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Abstract
A method of built-in self-testing field programmable gate arrays (FPGAs) including the programmable logic blocks, the programmable routing networks and the programmable input/output cells or boundary ports at the device, board or system level includes testing the programmable logic blocks, reconfiguring a first group of he programmable logic blocks to include a test pattern generator and an output response analyzer, and configuring the programmable routing network into groups of wires under test. This step is followed by generating test patterns propagated along the wires under test and comparing the outputs utilizing the output response analyzer. Based on the result of the comparison a pass/fail test result indication is routed to the associated boundary port. The results from a plurality of output response analyzers can be compared utilizing an iterative comparator in order to reduce the number of boundary ports required during testing.
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