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Abstract

A semiconductor fabrication method is provided for fabricating a capacitor with a low-resistance electrode structure in a mixed-mode integrated circuit (IC) device. The first step is to prepare a semiconductor substrate having a first area where a gate and a pair of source/drain regions are defined and a second area where a first electrode is defined. A first dielectric layer is then formed to cover the first electrode. After this, a doped polysilicon layer, a metal silicide layer, and a second dielectric layer are successively formed over the first dielectric layer, which in combination constitute a second electrode for the capacitor. The incorporation of the metal silicide layer in the second electrode can significantly help reduce the overall resistance of the second electrode, thereby allowing a considerable increase to the overall performance of the resulting IC device. Moreover, the method is less complex in process and thus easier to perform than the prior art.

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First Claim