Method to form transistors and local interconnects using a silicon nitride dummy gate technique

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United States of America Patent

PATENT NO 6204137
SERIAL NO

09556386

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Abstract

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A new method of forming MOS transistors has been achieved. A pad oxide layer is grown. A silicon nitride layer is deposited. Trenches are etched for planned STI. A trench liner is grown inside of the trenches. A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to complete the STI. The same silicon nitride layer is patterned to form dummy gates. A gate liner layer is deposited. Ions are implanted to form lightly doped drain junctions. Sidewall spacers are formed adjacent to the dummy gate electrodes and the shallow trench isolations. Ions are implanted to form the drain and source junctions. An epitaxial silicon layer is grown overlying the source and drain junctions. A metal layer is deposited. The epitaxial silicon layer is converted into sulicide to form silicided source and drain contacts. An interlevel dielectric layer is deposited and polished down to the dummy gates. The dummy gates are etched away to form openings for the planned transistor gates. A gate oxide layer is deposited lining the transistor gate openings. A gate electrode layer is deposited to fill the transistor gate openings. The gate electrode layer is patterned to complete the transistor gates.

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Patent Owner(s)

  • CHARTERED SEMICONDUCTOR MANUFACTURING LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chan, Lap San Francisco, CA 159 4793
Chen, Feng Singapore, SG 571 5974
See, Alex Singapore, SG 86 1439
Teo, Kok Hin Singapore, SG 6 92

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