Single electron transistor memory array
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United States of America Patent
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Mar 20, 2001
Grant Date -
N/A
app pub date -
Apr 9, 1998
filing date -
Apr 9, 1998
priority date (Note) -
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Abstract
A structure of a single-electron-transistor memory array is disclosed in the present invention. A substrate is provided. A buried oxide layer is on the substrate. A plurality of silicon wires are arranged on the buried oxide layer, wherein each of the silicon wires has a pair of ends. Oxynitride layers covers on the silicon wires. A polysilicon layer covers the oxynitride layers and the buried oxide layer. A source region and a drain region connect to a first end and a second end of each of the silicon wires, respectively.
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