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Abstract

An FPGA configuration circuit including a bus interface for applying a bit stream from either a JTAG interface or an input/output block (IOB) interface onto a bus. The bus interface parses a header word from the bit stream into an address field and an operand field. Several registers are connected to the bus including a frame data register, a frame address register, a control register, a command register, and an optional data check register. The bus interface generates control signals in response to the address field and the operand field that cause one or more registers to perform predefined operations according to subsequent data words in the bit stream. For example, during configuration write operations, the bus interface enables the frame data register to receive data signals that are subsequently transferred to a configuration memory array. Conversely, during configuration read operations, the frame data register is controlled to receive data from the configuration memory array, and to transfer the data to the bus interface. Partial reconfiguration is performed by storing the address of selected frames of the configuration memory array in the frame address register, which addresses the selected frames in the configuration memory array.

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