Importance

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Abstract

A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Each row has a plurality of adjacent horizontal conductors, and each column has a plurality of adjacent vertical conductors. The regions in a row are interspersed with groups of local conductors which interconnect the adjacent regions and the associated horizontal and vertical conductors. The local conductors can also be used for intra-region communication, as well as communication between adjacent regions. Secondary signals such as clocks and clears for the regions can be drawn either from dedicated secondary signal conductors or normal region inputs. Memory cell requirements for region input signal selection are reduced by various techniques for sharing these memory cells.

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First Claim