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Abstract

An input/output interconnect (IOI) circuit is provided for coupling input/output (IO) blocks to an array of configurable logic tiles in a field programmable gate array (FPGA). Each of the tiles includes a configurable logic block and a programmable interconnect structure that includes a plurality of intermediate-length buses. The intermediate-length buses are staggered, such that only a subset of the intermediate-length buses routed by a logic block is connected to the logic block. The IOI circuit includes routing circuits at the perimeter of the array for terminating the intermediate-length buses. In one embodiment, the routing circuits connect various ends of unidirectional intermediate-length buses in a U-turn configuration, thereby making use of all of the intermediate-length buses, and maintaining a regular pattern of intermediate-length buses in the tiles. In another embodiment, various ends of bi-directional intermediate-length buses are terminated to long lines through programmable interconnection points (PIPs). In another embodiment, PIPs are provided to enable horizontal long lines to be connected to horizontal intermediate-length buses, which in turn, can be connected to vertical long lines, thereby providing a low-skew, high fanout routing network.

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First Claim