Importance

Loading Importance Indicators...

Abstract

An ATM switch system has a plurality of input ports and output ports all having associated buffers, and a source traffic control system which includes a shared bus coupling the ports, and a switch controller or arbiter which controls the transfer of data among the ports via the shared bus. ATM cells placed on the shared bus include an internal destination address which designates the output port within the switch to which the ATM cell is destined. The switch controller monitors the internal destination addresses of the ATM cells, and increments a counter associated with the destination port when the destination corresponds, and decrements other counters which do not correspond to the destination. Accordingly, bursts for a particular output port causes the count of the associated counter to grow large; whereas frequent or long breaks cause the count to drop. The counts are compared to a high threshold which alerts the arbiter that the buffer of the output port being tracked is in danger of overflowing. Upon receiving the alert, the arbiter either stalls the bus by refusing to grant access to the bus until the counter decrements below the first threshold, or grants bus access to the input port associated with the output port on the theory that the input port will not be sending data to its own output. A low threshold is utilized to declare that a burst is over and to free the counter for tracking a new burst to the same or a different output port.

Loading the Abstract Image...

First Claim