Importance

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Abstract

A method of designing an LSI circuit pattern which connects a plurality of gates on an LSI chip. The method estimates a chip area of the LSI chip and a number of the plurality of gates required for achieving a desired function; estimates an interconnect length of each of the plurality of gates; designs a wiring pattern associated with the each of the plurality of gates based on a prescribed design rule, and calculates a gate delay time for the design wiring pattern; alters the design rule as necessary if the calculated gate delay time exceeds a prescribed target value, while calculating the total area occupied by the designed wiring patterns when the calculated gate delay time is within a prescribed target value. The process sequentially repeats for a gate having a next shortest interconnect length when the calculated total area occupied by the designed wiring patterns does not exceed the estimated chip area. When the calculated total area occupied by the designed wiring patterns exceeds the estimated chip area, add one new metal layer and sequentially repeat the process for the gate having a next shortest interconnect length on the added metal layer.

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First Claim